1. Field of the Invention
The present invention relates to semiconductor devices for use in various kinds of electric apparatuses and electronic apparatuses and a method for manufacturing the same.
2. Description of the Related Art
In recent years, the functions of semiconductor elements have been enhanced, and the size and the number of electrodes of each semiconductor element have been increased remarkably. On the other hand, with the demands for downsizing of electronic apparatuses, the request for downsizing semiconductor devices including semiconductor elements has been raised. Therefore, the type of packages of semiconductor devices has been changed from the quad flat package (QFP) type configured so that external electrodes are arranged in a periphery of a package, to the ball grid array (BGA) type configured so that external electrodes are arranged in an area array style on a lower face of a package, and the chip scale package (CSP) type.
FIG. 19 illustrates an example of a semiconductor device of the CSP type. As shown in FIG. 19, a semiconductor element 1000 including electrode parts (not shown), and a wiring substrate 1003 including electrodes 1002 for connection with the electrode parts (hereinafter referred to as electrode-part-connection electrodes) are connected electrically via bumps 1001, and the area in which they are connected (hereinafter referred to as connection portion) is encapsulated with a resin forming a resin layer 1004. The resin layer 1004 homogeneously disperses stresses occurring due to a difference between the thermal expansion of the semiconductor element 1000 and that of the wiring substrate 1003, thereby preventing the connection portion between the electrode parts and the electrode-part-connection electrodes 1002 from being damaged. External electrodes 1005 are provided on a face of the wiring substrate 1003 opposite to the semiconductor element side face thereof.
A semiconductor device in which electrode parts of a semiconductor element and electrode-part-connection electrodes of a wiring substrate are connected by metal joint via bumps has been disclosed already (see, for instance, in JP 9(1997)-181119 A, and JP 2002-151551A).
Further, in recent years, a so-called wafer level packaging technology, whereby a plurality of semiconductor elements are packaged together at a wafer level, has been proposed. FIG. 20 shows an example of a semiconductor device manufactured by the wafer level packaging technology. As shown in FIG. 20, a semiconductor element 2000 includes an electronic circuit and electrode pads that are formed on a semiconductor substrate, and bumps 2001 are formed on the electrode pads. The bumps 2001, except for ends thereof, are encapsulated with a resin layer 2002, and the ends of the bumps 2001 function as external electrodes. The resin layer 2002 functions in the same manner as the resin layer 1004 of the semiconductor device shown in FIG. 19 does (see, for instance, JP 10(1998)-79362 A).
However, the conventional semiconductor devices shown in FIGS. 19 and 20 have the following problems. The reduction of stresses by the resin layer 1004 or 2002 cannot be regarded as sufficient, and when reliability such as resistance against thermal shock is evaluated, for instance, the resin layers 1004 and 2002 are prone to the cracking. Further, since the bumps 1001 or 2001 are formed and the connection portion between the semiconductor element and the wiring substrate is encapsulated with the resin layer 1004 or 2002, the manufacturing cost and the number of steps in the manufacturing process increase. Still further, the semiconductor devices shown in FIGS. 19 and 20 both include bumps 1001 and 2001, respectively, and such a configuration hinders the reduction of the thickness of the semiconductor device.